Design A 1 Bit Serial Adder Computer Science Essay The main aim of this project is to design a 1-bit serial adder, simulate its functionality and obtain a layout on silicon, using the 0.35µ process from AMS. The circuit designed shows a working serial adder clocking at (100MHz of nsecs) with a delay of 0.56910nsec. The area of the layout is 99.3016.35 µm2 in this technology. The circuit performs an 8-bit addition in 0.569108 nsesc. The circuit uses a standard 1-bit full adder and it has a feedback loop using a D-flip-flop in order to transmit the carry bit to the next input value. The final layout product has 3-input pads and 2-output pads, with power and ground pads. The process known as serial addition of binary numbers is well known in the computing and units capable of performing such serial binary addition ordinarily comprise a basic portion of more complex computation devices.
